This invention relates generally to a semiconductor integrated circuit device, and more particularly to a master chip system which will be suitable for a gate array LSI with a built-in memory circuit group.
"PROCEEDING OF IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN", 1984, pp 424-427 is known as the reference on the gate array with a built-in 3-port RAM having a changeable structure. However, this prior art reference does not deal with the problem of the wiring method of RAM data in the gate array and does not mention, either, the problems resulting from the changeable RAM structure and its changing method.
In other words, since the prior art technique described above does not take wiring of RAM data into consideration, it is not free from the problems of the drop of the RAM speed and the trouble of wiring depending on the place of use of the RAM data.